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篇目详细内容 |
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【篇名】 |
Iterative hybrid decoding algorithm for LDPC codes based on attenuation factor |
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【刊名】 |
Frontiers of Electrical and Electronic Engineering |
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【刊名缩写】 |
Front. Electr. Electron. Eng. |
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【ISSN】 |
2095-2732 |
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【EISSN】 |
2095-2740 |
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【DOI】 |
10.1007/s11460-012-0195-x |
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【出版社】 |
Higher Education Press and Springer-Verlag Berlin
Heidelberg |
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【出版年】 |
2012 |
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【卷期】 |
7
卷3期 |
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【页码】 |
279-285
页,共
7
页 |
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【作者】 |
Minghua LIU;
Lijun ZHANG;
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【关键词】 |
attenuation factor; reliability-based; iterative; majority-logic; low-density parity-check (LDPC) codes |
【摘要】 |
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An attenuated iterative reliability-based majority-logic (AIML) decoding algorithm for low-density parity-check (LDPC) codes is proposed, which pertains to hybrid decoding schemes. The algorithm is devised based on the orthogonal check-sums of one-step majority-logic (OSMLG) decoding algorithm in conjunction with certain of reliability measures of the received symbols. Computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that, in binary-input additive white Gaussian noise (BI-AWGN) channel, the AIML decoding algorithm outperforms other popular iterative reliability-based majority-logic (IML) decoding algorithms with a slight increase in computational complexity. Within maximum iteration number of 5, the AIML algorithm can achieve almost identical error performance to sum-product algorithm (SPA). No error floor effect can be observed for the AIML algorithm down to the bit error rate (BER) of , while error floor appears for SPA around the BER of even with maximum iteration number of 100. Furthermore, the inherent feature of parallel procession for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping (WBF) algorithm. |
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